Mailing List Archive: Xen: Devel

[PATCH 7/7] Nested VMX: Clear APIC-v control bit in vmcs02

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yang.z.zhang at intel

Aug 9, 2013, 1:49 AM

Post #1 of 4 (14 views)
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[PATCH 7/7] Nested VMX: Clear APIC-v control bit in vmcs02

From: Yang Zhang <yang.z.zhang [at] Intel>

There is no vAPIC-v supporting, so mask APIC-v control bit when
constructing vmcs02.

Signed-off-by: Yang Zhang <yang.z.zhang [at] Intel>
---
xen/arch/x86/hvm/vmx/vvmx.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 9ba169d..eed09be 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -617,6 +617,8 @@ void nvmx_update_secondary_exec_control(struct vcpu *v,
shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, SECONDARY_VM_EXEC_CONTROL);
nvmx->ept.enabled = !!(shadow_cntrl & SECONDARY_EXEC_ENABLE_EPT);
shadow_cntrl |= host_cntrl;
+ shadow_cntrl &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
__vmwrite(SECONDARY_VM_EXEC_CONTROL, shadow_cntrl);
}

@@ -627,6 +629,7 @@ static void nvmx_update_pin_control(struct vcpu *v, unsigned long host_cntrl)

shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL);
shadow_cntrl |= host_cntrl;
+ shadow_cntrl &= ~PIN_BASED_POSTED_INTERRUPT;
__vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl);
}

--
1.7.1

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andrew.cooper3 at citrix

Aug 9, 2013, 3:50 AM

Post #2 of 4 (11 views)
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Re: [PATCH 7/7] Nested VMX: Clear APIC-v control bit in vmcs02 [In reply to]

On 09/08/13 09:49, Yang Zhang wrote:
> From: Yang Zhang <yang.z.zhang [at] Intel>
>
> There is no vAPIC-v supporting, so mask APIC-v control bit when
> constructing vmcs02.
>
> Signed-off-by: Yang Zhang <yang.z.zhang [at] Intel>
> ---
> xen/arch/x86/hvm/vmx/vvmx.c | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
> index 9ba169d..eed09be 100644
> --- a/xen/arch/x86/hvm/vmx/vvmx.c
> +++ b/xen/arch/x86/hvm/vmx/vvmx.c
> @@ -617,6 +617,8 @@ void nvmx_update_secondary_exec_control(struct vcpu *v,
> shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, SECONDARY_VM_EXEC_CONTROL);
> nvmx->ept.enabled = !!(shadow_cntrl & SECONDARY_EXEC_ENABLE_EPT);
> shadow_cntrl |= host_cntrl;
> + shadow_cntrl &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
> + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);

Alignment again, but otherwise ok.

~Andrew

> __vmwrite(SECONDARY_VM_EXEC_CONTROL, shadow_cntrl);
> }
>
> @@ -627,6 +629,7 @@ static void nvmx_update_pin_control(struct vcpu *v, unsigned long host_cntrl)
>
> shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL);
> shadow_cntrl |= host_cntrl;
> + shadow_cntrl &= ~PIN_BASED_POSTED_INTERRUPT;
> __vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl);
> }
>

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JBeulich at suse

Aug 9, 2013, 5:37 AM

Post #3 of 4 (10 views)
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Re: [PATCH 7/7] Nested VMX: Clear APIC-v control bit in vmcs02 [In reply to]

>>> On 09.08.13 at 10:49, Yang Zhang <yang.z.zhang [at] intel> wrote:
> --- a/xen/arch/x86/hvm/vmx/vvmx.c
> +++ b/xen/arch/x86/hvm/vmx/vvmx.c
> @@ -617,6 +617,8 @@ void nvmx_update_secondary_exec_control(struct vcpu *v,
> shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, SECONDARY_VM_EXEC_CONTROL);
> nvmx->ept.enabled = !!(shadow_cntrl & SECONDARY_EXEC_ENABLE_EPT);
> shadow_cntrl |= host_cntrl;
> + shadow_cntrl &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
> + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
> __vmwrite(SECONDARY_VM_EXEC_CONTROL, shadow_cntrl);
> }
>
> @@ -627,6 +629,7 @@ static void nvmx_update_pin_control(struct vcpu *v,
> unsigned long host_cntrl)
>
> shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL);
> shadow_cntrl |= host_cntrl;
> + shadow_cntrl &= ~PIN_BASED_POSTED_INTERRUPT;
> __vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl);
> }
>

I can see why you want to mask the bit off of host_cntrl, but is it
really correct to also mask it when set in the vVMCS? Shouldn't
that rather result in a fault raised to it? (If that's already the case
- I just don't know the nested code well enough yet - then this
would still call for being adjusted logically: Mask the bit when or-ing
in host_cntrl, and assert that the bit is clear in what you read from
vVMCS. This would make much more obvious what the intentions
here are.

Jan

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yang.z.zhang at intel

Aug 10, 2013, 8:04 PM

Post #4 of 4 (9 views)
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Re: [PATCH 7/7] Nested VMX: Clear APIC-v control bit in vmcs02 [In reply to]

Jan Beulich wrote on 2013-08-09:
>>>> On 09.08.13 at 10:49, Yang Zhang <yang.z.zhang [at] intel> wrote:
>> --- a/xen/arch/x86/hvm/vmx/vvmx.c
>> +++ b/xen/arch/x86/hvm/vmx/vvmx.c
>> @@ -617,6 +617,8 @@ void nvmx_update_secondary_exec_control(struct
> vcpu *v,
>> shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx,
>> SECONDARY_VM_EXEC_CONTROL); nvmx->ept.enabled = !!(shadow_cntrl &
>> SECONDARY_EXEC_ENABLE_EPT); shadow_cntrl |= host_cntrl;
>> + shadow_cntrl &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
>> + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
>> __vmwrite(SECONDARY_VM_EXEC_CONTROL, shadow_cntrl); }
>> @@ -627,6 +629,7 @@ static void nvmx_update_pin_control(struct vcpu
>> *v, unsigned long host_cntrl)
>>
>> shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx,
>> PIN_BASED_VM_EXEC_CONTROL); shadow_cntrl |= host_cntrl; +
>> shadow_cntrl &= ~PIN_BASED_POSTED_INTERRUPT;
>> __vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl); }
>
> I can see why you want to mask the bit off of host_cntrl, but is it
> really correct to also mask it when set in the vVMCS? Shouldn't that
> rather result in a fault raised to it? (If that's already the case
> - I just don't know the nested code well enough yet - then this would
> still call for being adjusted logically: Mask the bit when or-ing in
> host_cntrl, and assert that the bit is clear in what you read from
> vVMCS. This would make much more obvious what the intentions here are.
Sure, it sounds much reasonable.

>
> Jan

Best regards,
Yang

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